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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual ECL Output Comparator With Latch
The MC10E1651 is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using Motorola's advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENa and LENb) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met.
MC10E1651
DUAL ECL OUTPUT COMPARATOR WITH LATCH
* * * * * * *
Typ. 3.0 dB Bandwidth > 1.0 GHz Typ. V to Q Propagation Delay of 775 ps Typ. Output Rise/Fall of 350 ps Common Mode Range -2.0 V to +3.0 V Individual Latch Enables Differential Outputs 28mV Input Hysteresis
FN SUFFIX PLASTIC PACKAGE CASE 775-02
L SUFFIX CERAMIC PACKAGE CASE 620-10
LOGIC DIAGRAM
V1a Qa V2a LENa Qa LEN H H L V1, V2 V1 > V2 V1 < V2 X Function H L Latched
FUNCTION TABLE
V1b Qb V2b LENb Qb
VEE = -5.2 V VCC = +5.0 V
12/93
(c) Motorola, Inc. 1996
2-1
REV 1
MC10E1651
Pinout: 20-Lead PLCC (Top View)
Qb LENb NC 18 Qb GND NC GND Qa 19 20 1 2 3 4 5 6 7 V2a 8 V1a 17 16 V1b 15 V2b 14 13 12 11 10 9 VCC NC NC VEE VCC
Pinout: 16-Pin Ceramic DIP (Top View)
GND Qb 16 15
Qb LENb V1b V2b VCC 14 13 12 11 10
NC 9
1
2
3
4
5
6
7
8 VEE
GND Qa
Qa LENa V2a
V1a VCC
Qa LENa NC
ABSOLUTE MAXIMUM RATINGS (Beyond which device life may be impaired)
Symbol VSUP VPP Total Supply Voltage |VEE| + |VCC| Differential Input Voltage |V1 - V2| Characteristic Min Typ Max 12.0 V 3.7 Unit V
DC CHARACTERISTICS (VEE = -5.2 V 5%; VCC = +5.0 V 5%)
0C Symbol VOH VOL II IIH ICC IEE VCMR Hys Vskew Cin Characteristic Output HIGH Voltage Output Low Voltage Input Current (V1, V2) Input HIGH Current (LEN) Positive Supply Current Negative Supply Current Common Mode Range Hysteresis Hysteresis Skew Input Capacitance DIP PLCC -2.0 27 -1.0 3 2 Min -1020 -1950 Typ Max -840 -1630 65 150 50 -55 3.0 -2.0 27 -1.0 3 2 Min -980 -1950 25C Typ Max -810 -1630 65 150 50 -55 3.0 -2.0 30 0 3 2 Min -920 -1950 85C Typ Max -735 -1600 65 150 50 -55 3.0 Unit mV mV A mA V mV mV pF 1 Condition
1. Hysteresis skew (Vskew) is provided to indicate the offset of the hysteresis window. For example, at 25C the nominal hysteresis value is 27mV and the Vskew value indicates that the hysteresis was skewed from the reference level by 1mV in the negative direction. Hence the hysteresis window ranged from 14mV below the reference level to 13mV above the reference level. All hysteresis measurements were determined using a reference voltage of 0mV.
MOTOROLA
2-2
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E1651
AC CHARACTERISTICS (VEE = -5.2 V 5%; VCC = +5.0 V 5%)
0C Symbol tPLH tPHL ts th tpw tskew TDE Characteristic Propagation Delay to Output V to Q LEN to Q Setup Time V Enable Hold Time V Minimum Pulse Width LEN Within Device Skew Delay Dispersion (ECL Levels) Delay Dispersion (TTL Levels) Rise/Fall Times 20-80% Min 600 400 450 -50 400 15 Typ 750 575 300 -250 Max 900 750 Min 625 400 450 -50 400 15 100 60 ps 350 100 ps 225 325 475 225 325 475 250 375 500 6, 7 5, 6 25C Typ 775 575 300 -250 Max 925 750 Min 700 500 550 -100 400 15 ps ps 3, 4 3, 5 2 85C Typ 850 650 350 ps -250 ps Max 1050 850 ps Unit ps Condition 1
TDL
tr tf
1. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. For propagation delay measurements the threshold level (VTHR) is centered about an 850mV input logic swing with a slew rate of 0.75 V/NS. There is an insignificant change in the propagation delay over the input common mode range. 2. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions. 3. Refer to figure 4 and note that the input is at 850mV ECL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 4. The slew rate is 0.25 V/NS for input rising edges. 5. The slew rate is 0.75 V/NS for input rising edges. 6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 7. The slew rate is 0.3 V/NS for input rising edges.
APPLICATIONS INFORMATION
The timing diagram (Figure 3) is presented to illustrate the MC10E1651's compare and latch features. When the signal on the LEN pin is at a logic high level, the device is operating in the "compare mode," and the signal on the input arrives at the output after a nominal propagation delay (tPHL, tPLH). The input signal must be asserted for a time, ts, prior to the negative going transition on LEN and held for a time, th, after the LEN transition. After time th, the latch is operating in the "latch mode," thus transitions on the input do not appear at the output. The device continues to operate in the "latch mode" until the latch is asserted once again. Moreover, the LEN pulse must meet the minimum pulse width (tpw) requirement to effect the correct input-output relationship. Note that the LEN waveform in Figure 3 shows the LEN signal swinging around a reference labeled VBBINT; this waveform emphasizes the requirement that LEN follow typical ECL 10KH logic levels because VBBINT is the internally generated reference level, hence is nominally at the ECL VBB level. Finally, VOD is the input voltage overdrive and represents the voltage level beyond the threshold level (VTHR) to which the input is driven. As an example, if the threshold level is set on one of the comparator inputs as 80mV and the input signal swing on the complementary input is from zero to 100mV, the positive going overdrive would be 20mV and the negative going overdrive would be 80mV. The result of differing overdrive levels is that the devices have shorter propagation delays with greater overdrive because the threshold level is crossed sooner than the case of lower overdrive levels. Typically, semiconductor manufactures refer to the threshold voltage as the input offset voltage (VOS) since the threshold voltage is the sum of the externally supplied reference voltage and inherent device offset voltage.
ECLinPS and ECLinPS Lite DL140 -- Rev 4
2-3
MOTOROLA
MC10E1651
VBBINT LEN ts V VIN VTHR tPLH(LEN) VOD th tpw
tPHL Q
Q
Figure 3. Input/Output Timing Diagram
DELAY DISPERSION
Under a constant set of input conditions comparators have a specified nominal propagation delay. However, since propagation delay is a function of input slew rate and input voltage overdrive the delay dispersion parameters, TDE and TDT, are provided to allow the user to adjust for these variables (where TDE and TDT apply to inputs with standard ECL and TTL levels, respectively). Figure 4 and Figure 5 define a range of input conditions which incorporate varying input slew rates and input voltage overdrive. For input parameters that adhere to these constraints the propagation delay can be described as: TNOM TDE (or TDT) where TNOM is the nominal propagation delay. TNOM accounts for nonuniformity introduced by temperature and voltage variability, whereas the delay dispersion parameter takes into consideration input slew rate and input voltage overdrive variability. Thus a modified propagation delay can be approximated to account for the effects of input conditions that differ from those under which the parts where tested. For example, an application may specify an ECL input with a slew rate of 0.25 V/NS, an overdrive of 17mV and a temperature of 25C, the delay dispersion parameter would be 100 ps. The modified propagation delay would be 775ps 100ps
-0.9 V - 1.07 V INPUT THRESHOLD RANGE - 1.58 V - 1.75 V SLEW RATE = 0.25 V/NS SLEW RATE = 0.75 V/NS
2.5 V 2.0 V INPUT THRESHOLD RANGE 0.5 V 0V SLEW RATE = 0.30 V/NS SLEW RATE = 0.75 V/NS
Figure 4. ECL Dispersion Test Input Conditions
Figure 5. TTL Dispersion Test Input Conditions
MOTOROLA
2-4
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E1651
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B D -L-MW D V X VIEW D-D A Z R 0.007 (0.180) M T L -M
S
-N-
Y BRK
0.007 (0.180) M T L -M U
S
N
S S
0.007 (0.180) M T L -M
N
S
Z
20
1
G1
0.010 (0.250) S T L -M
S
N
S
0.007 (0.180) M T L -M
S
N
S
N
S
H
0.007 (0.180) M T L -M
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1 K F VIEW S 0.007 (0.180) M T L -M
S
J
-T-
SEATING PLANE
VIEW S T L -M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.310 0.330 0.040 --
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 -- 0.50 2 10 7.88 8.38 1.02 --
ECLinPS and ECLinPS Lite DL140 -- Rev 4
2-5
MOTOROLA
MC10E1651
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G J K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-B1 8
C
L
-TSEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
T
A
S
MOTOROLA
2-6
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E1651
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
ECLinPS and ECLinPS Lite DL140 -- Rev 4 2-7
*MC10E1651/D*
MC10E1651/D MOTOROLA

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